Although the integrated circuit market is dominated by field effect transistors, bipolar transistors are still of considerable interest because, for example, their operating speeds are typically higher than are the operating speeds of field effect transistors. As device dimensions decrease, due to a desire for still higher operating speeds as well as greater packing densities, fabrication of bipolar, as well as field effect, transistors becomes more difficult. For example, a high speed bipolar transistor requires fabrication of a small base region which must not only be electrically contacted but must also be accurately aligned with respect to both the emitter and collector regions. A small base region is desirable because it reduces the emitter-base capacitance which is one of the factors limiting device operating speed. Additionally, a small base width improves device response time. It will also be appreciated that electrical contacts to both the emitter and collector regions must also be fabricated which are small and have low resistance. Similar fabrication problems also arise as the dimensions of field effect transistors decrease.
Numerous techniques have been devised for fabricating bipolar transistors. See, for example, U.S. Pat. Nos. 3,833,429 issued on Sept. 3, 1974 and 4,338,138 issued on July 6, 1982 for illustrative techniques. These and other fabrication techniques have been developed to a level of sophistication such that bipolar transistors with submicron feature sizes have been fabricated. For example, an illustrative bipolar transistor with submicron features is described in International Electron Devices Meeting, 1985, paper 2.1, pp. 18-21. The technique described by the authors is termed "The Supper Self-Aligned Process Technology, i.e., SST. The fabrication technique is relatively complicated although only a single patterning step using an optical mask is said to be required. Many materials, e.g., silicon dioxide, silicon nitride and polysilicon, are used, but the typical sequence for each material used comprises depositing the material and then selectively etching it to form the desired pattern with perhaps an intermediate oxidation step. The fabrication sequence is depicted in his FIG. 2 and the device in his FIG. 1.
Although useful SST devices were apparently fabricated, there are some undesirable limitations to the described technique which also impose limitations on the characteristics of the device disclosed. For example, while the disclosed technique can probably produce feature sizes as small as 0.20 .mu.m, the scaled down dimension of the emitter region, variations in the etch rate may prohibit a further reduction of the feature sizes by as much as an order of magnitude. Additionally, the distance between the base and emitter metal contacts is determined by optical photolithographic and etching technique limitations. The resulting relatively large spacing shown in FIG. 1 is undesirable because the sheet resistance of the polysilicon used for the base contact is an important factor in determining the extrinsic base resistance. The extrinsic base resistance for the disclosed device will be relatively high thus resulting in increased noise, i.e., it acts as a noise source connected to the base.
It will also be appreciated by those skilled in the art that control of the polysilicon sheet resistance will be relatively difficult because the polysilicon grain size is a function of the deposition parameters, annealing conditions, etc., and these parameters may be difficult to control precisely in practice. Variations in both the carrier mobility in the polysilicon film and the extrinsic base resistance may result in variations in device operating characteristics.
Another limitation arises because doped polysilicon is used as the diffusion source to form the junction between the base and emitter. Process control problems will almost certainly result because the emitter profile is determined by the surface conditions at the single crystal/polycrystalline interface. It is known to those skilled in the art that several layers of an oxide at this interface may dramatically change the emitter profile due to surface segregation effects.
It is apparent that many of the limitations described with respect to device performance might be avoided with a fabrication technique that permits fabrication of features with dimensions smaller than the minimum feature size permitted by direct patterning.